Chapter3 Preparing Design Files for Synthesis.

Organizing the Design Data.

 

• Establishing and adhering to a method of organizing data are more important than the method you choose.

 

 

 

Partitioning for Design Reuse

 

• Design reuse decreases time to market by reducing the design, integration and testing effort.

1. Thoroughly define and document the design interface.
2. Standardize interfaces whenever possible.
3. Parameterize the HDL code.

 

 

Keeping Related Combinational Logic Together

 

• Dividing related combinational logic into separate blocks introduces artificial barriers that restrict logic optimization.

1. Group related combinational logic and its destination register together.

-> DC has the flexibility to merge logic, resulting in a smaller, faster design.

조합회로와 레지스터를 묶으라는 뜻입니다.

 

2. Eliminate glue logic.

 

glue 로직이란 복잡한 조합회로가 서로 연결되있는 것을 말합니다.

 

 

 

 

 

Registering Block Outputs

 

• This method enables you to constrain each block easily because
•  The drive strength on the inputs to an individual block always equals the drive strength of the average input drive.
•  The input delays from the previous block always equal the path delay through the flip-flop.

 

 

 

 

Partitioning by Design Goal

 

When certain parts of a design are more area and timing critial than other parts.

•  Isolate the Two type.

           1. Noncritical speed constraint logic

           2. Critical speed constraint logic

 

 

 

 

Partitioning by Compile Technique

 

When the design contains highly structured logic along with random logic.

•  Isolate the Two type.

           1. Highly structured logic. ex) error detection circuitry

           → Use the Structuring Technique.

           ► Result : Reduced design area.

           2. Random logic.

           → Use the Flattening Technique.

           ► Result : Reduced speed optimization.

          

 

 

1. Structuring Technique

           Adds intermediate variables and thus logic structure.

 

 

2. Flattening Technique

           Goal is to create a 2 level S.O.P.

           Two edged sword:

                     Remove bad structure.

                     Remove good structure as well.

          

 

오른쪽을 왼쪽처럼 바꾸는 것입니다.

 

 

 

 

 

Keeping Sharable Resources Together

 

Design Compiler can share large resources such as adder or multiplier.

•   Caution !  Only if the resources belong to same Always block.

 

 

 

 

 

Keeping User-Defined Resources With the Logic They Drive

 

Design Compiler cannot automatically share or create multiple instances of user-defined resources.

Inserting multiple instiations of User-Defined Resources by manually.

 

 

 

Writing technology-independent HDL

 

1. Inferring Multiplexers

           HDL Compiler can infer a generic multiplexer cell(MUX_OP) from case statements in your HDL code.

 

 

 

2.   Inferring Registers & Mixing Register Types

           HDL Compiler infers a D flip-flop whenever the sensitivity list of a Verilog always block.

           If the target library have not a D-latch, DC synthesizes the combinational logic.

 

 

 

 

 

 

3.        Inferring Three-State Drivers

           Assign the high-impedance value to the output pin to have DC infer three-state gates.

           HDL Compiler는 조건문에서 high-impedance 값을 항상 false로 한다.

 

 

 

 

 

 

 

 

 

 

4.        Inferring Multibit Components

           Multibit inference allows you to map registers, mux and three-state cells to regularly structured logic or multibit library cells.

 

 

 

 

 

 

5. Designing State Machines

     1) State minimization can be performed.

     2) Tradeoffs between different encoding styles can be made.(ex Gray encoding)

     3) Don’t care conditions can be used without flattening the design.

     4) Don’t care state codes are automatically derived.

 

 

Using HDL Constructs

 

1. Sensitivity Lists

           You should completely specify the sensitivity list for each always block.

 

 

 

 

2. Value Assignments

           Use nonblocking assignments(<=) within sequential Verilog always block.

           Use blocking assignments(=) within combinational Verilog always block.

 

3.        if Statements

           if만 쓰고 else 항목을 쓰지 않으면 latch가 생긴다.

 

 

4.        case Statements

           case 문에는 반드시 default를 써서 latch의 발생을 예방하자.

 

 

 

 

5.        Constant Definitions

           Use the Verilog `define statement.